a family of instruction set architectures(ISA) developed by Intel
32-bit ISA ↔ IA-32 ↔ i386
for RISC-V CS61C

Assembly

incl increse 1

imul multiply

popal restores ALL the registers (including ebp) from the ones that were saved on the stack you're switching to

int f( int );

int main (void)
{
  int x;
  asm volatile("movl $3,%0" :"=g"(x): :"memory"); // x = 3; (output)
  printf("%d  ->  %d\\n",x,f(x));
}

/*END   Main    */

int f( int x )
{
   asm volatile("movl %0,%%eax
                 imull $3, %%eax
                 addl $4,%%eax"
         :
         :"a" (x)
         : "eax", "memory"
        ); //return (3*x + 4);  (input)
}

/*
+---+--------------------+
| r |    Register(s)     |
+---+--------------------+
| a |   %eax, %ax, %al   |
| b |   %ebx, %bx, %bl   |
| c |   %ecx, %cx, %cl   |
| d |   %edx, %dx, %dl   |
| S |   %esi, %si        |
| D |   %edi, %di        |
+---+--------------------+
*/

Registers

General purpose registers (GPR) store both data and addresses

`ax`	Accumulator	I/O port access, arithmetic, interrupt calls
`bx`	Base	Base pointer for memory access
`cx`	Counter	Loop counting, bit shifts
`dx`	Data	I/O port access, arithmetic, interrupt calls
`sp`	Stack Pointer	Top address of stack
`bp`	Base Pointer	Base address of stack
`si`	Source Index	Source for stream operations (e.g. string)
`di`	Destination Index	Destination for stream operations (e.g. string)

Instruction pointer(ip) register holds address of next instruction to execute
Started as 16-bits, extend to 32-bit using e prefix (e.g. eax for ax), 64-bit using r prefix
CR2: Page Fault Linear Address(PFLA)
CR3: page table base register(PTBR)
Segment
- CS-code segment, DS-data segment, …
- Typical Segment Register. Current Priority is RPL of Code Segment (CS)

https://wiki.osdev.org/CPU_Registers_x86

AT&T Syntax

register like %eax, constant like $4
address memory: offset(base, index, scale)
- base, index for registers
- scale in [1,2,4,8]
- address=base+index*scale+offset